This is a 32-bit Single-Cycle RISC-V Processor implementing the RV32IM Instruction Set Architecture.
This project was built as a learning experience to understand how a processor works internally. The design is kept simple, modular, and easy to understand, making it ideal for students and beginners exploring CPU architecture.
The processor supports the RV32I base instruction set along with the RV32M multiplication and division extension.
- RV32I Base ISA support
- RV32M Multiply/Divide support
- Single-cycle architecture
- Modular Verilog design
- Byte-addressable data memory
- Branch and jump support
- Load/store instructions
- Signed and unsigned operations
- Fully synthesizable RTL
- ADD, SUB
- ADDI
- SLT, SLTU
- SLTI, SLTIU
- AND, OR, XOR
- ANDI, ORI, XORI
- SLL, SRL, SRA
- SLLI, SRLI, SRAI
- LW, LH, LB
- LHU, LBU
- SW, SH, SB
- BEQ, BNE
- BLT, BGE
- BLTU, BGEU
- JAL
- JALR
- LUI
- AUIPC
- MUL
- MULH
- MULHU
- MULHSU
- DIV
- DIVU
- REM
- REMU
The processor consists of the following modules:
- Program Counter
- Instruction Memory
- Register File (32 × 32-bit)
- ALU (RV32IM supported)
- ALU Control Unit
- Main Control Unit
- Sign Extend Unit
- Data Memory
- Branch Logic
All instructions execute in a single clock cycle.
- Arithmetic test program
- Sorting algorithm (Bubble Sort)
- Factorial computation
- Convolution (DSP workload)
- Branch stress test
- Load/store memory test
├── alu.v ├── aluControl.v ├── controlUnit.v ├── registerFile.v ├── programCounter.v ├── instructionMemory.v ├── dataMemory.v ├── signExtend.v ├── multiplier.v ├── divider.v ├── top.v └── testbench.sv
- Pipelined version
- Hazard detection
- Forwarding unit
- RV32C support
- CSR registers
- Interrupt support
- Cache memory
Anish Rooj
Electronics & Telecommunication Engineering
Jadavpur University
LinkedIn:
www.linkedin.com/in/anish-rooj
This project is open-source and free to use for educational purposes.