Namespace all common_cells modules with a cc_ prefix #290
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Namespace all common_cells modules with a cc_ prefix #290
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Prefix all SystemVerilog module names and corresponding source files with `cc_` throughout src/, test/, and formal/ directories, including module declarations, instantiations, and deprecated modules. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Update Bender.yml, common_cells.core, src_files.yml, and Makefile to use the new cc_-prefixed source file names. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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TODOs
simulate.sha legacy script or should it be updated/added to the CI?